#ifndef GICV3_REG_H
#define GICV3_REG_H

//
// Distributor layout
//
#define GICD_CTLR      0x0000
#define GICD_TYPER     0x0004
#define GICD_IIDR      0x0008
#define GICD_TYPER2    0x000C
#define GICD_STATUSR   0x0010

/*
 *  0x0014-0x001C
 *  0x0020-0x003C
 */

#define GICD_SETSPI_NSR   0x0040
#define GICD_CLRSPI_NSR   0x0048
#define GICD_SETSPI_SR    0x0050
#define GICD_CLRSPI_SR    0x0058

/*
 *  0x005C-0x007C
 */

#define GICD_IGROUP0   0x0080
#define GICD_ISENABLE  0x0100
#define GICD_ICENABLE  0x0180
#define GICD_ISPEND    0x0200
#define GICD_ICPEND    0x0280
#define GICD_ISACTIVE  0x0300
#define GICD_ICACTIVE  0x0380
#define GICD_IPRIORITY 0x0400
#define GICD_ITARGETS  0x0800
#define GICD_ICFG      0x0c00
#define GICD_IGRPMODER 0x0D00
#define GICD_NSACR     0x0E00
#define GICD_SGIR      0x0F00
#define GICD_CPENDSGIR 0x0F10
#define GICD_SPENDSGIR 0x0F20

#define GICD_INMIR     0x0F80


//
// GIC Redistributor Register
//
#define GICR_CTRLR     0x0000
#define GICR_IIDR      0x0004
#define GICR_TYPER     0x0008
#define GICR_STATUSR   0x0010
#define GICR_WAKER     0x0014
#define GICR_MPAMIDR   0x0018

#define GICR_PROPRASER 0x0070
#define GICR_PENDBASER 0x0078
#define GICR_INVALLR   0x00B0

//
// CPU Interface layout
//
#define GICC_CTLR      0x0000
#define GICC_PMR       0x0004
#define GICC_BPR       0x0008
#define GICC_IAR       0x000c
#define GICC_EOIR      0x0010
#define GICC_RPR       0x0014
#define GICC_HPPIR     0x0018
#define GICC_ABPR      0x001c
#define GICC_AIAR      0x0020
#define GICC_AEOIR     0x0024
#define GICC_AHPPIR    0x0028
#define GICC_APR0      0x00d0
#define GICC_NSAPR0    0x00e0
#define GICC_IIDR      0x00fc
#define GICC_DIR       0x1000

#endif